1. Technical Field of the Invention
The present invention relates to memory devices, and more particularly to a memory control system using a dummy bit line sensing scheme for providing power down timing and a bit line offset voltage for timing margin control to reduce power consumption.
2. Description of the Related Art
Memory devices typically include an array or matrix of memory cells for storage and retrieval of data, where the array of memory cells are arranged in rows and columns. Although many architectures are possible, a row or word line decoder including a plurality of word line drivers and a column decoder are provided for decoding an address for accessing a particular location of the memory array. Sense amplifiers are enabled to sense the data from the memory cells in the array. It is desired to shut down the data sense amplifiers as soon as possible since they consume appreciable power while activated. Various methods are known for achieving low power dissipation, many of which include self-timing schemes. Most of these schemes, however, are not operable or reliable at reduced power supply voltages, do not provide the means for timing margin control and are not designed to reduce power across the wide range of memory configurations required for a compiler application.
Many designs are not self-timed and thus depend upon a subsequent clock edge for termination of the cycle. Such clock dependence restricts the clock duty cycle and potentially dissipates more power since the sense amplifiers of the memory array remain active longer than necessary. Other self-timing schemes do not closely track the core memory array read/write sense, thereby resulting in a longer access cycle time and increased power dissipation. Self-timing sensing schemes are also known for memory compilers. However, known compiler self-timing schemes are often designed to operate correctly for a wide range of memory sizes and thus are based on the worst case or largest size configuration only. These schemes are often not designed to track the size and thus do not optimize power usage for all possible configurations, particularly for smaller memory arrays. Another self-timing scheme includes no timing margin control to assure that the core memory array access is completed before power down is initiated, often resulting in memory errors.
Most of the known sensing schemes are not operable or reliable at low power supply voltages below 2.0 volts, and thus require higher voltage and power levels. It is desired to provide a synchronous memory with low power architecture and with self-timing margin control to reduce power usage across a wide range of memory configurations required for a compiler application. It is also desired that the memory operate correctly at lower voltage levels, such as 1.8 volts or less.